(1) Field of the Invention
This invention relates to a semiconductor device and, more particularly, to a semiconductor device which can transmit data having a bus width wider than the width of an external data bus.
(2) Description of the Related Art
With devices of a command input type represented by synchronous dynamic random access memories (DRAMs), usually data and a command are sent at the same time and are got at the leading edge of a system clock. A method under which data is got only once at the leading edge of a clock in this way is called a single data rate (SDR) type. Now, an example of a circuit for transferring data in a synchronous device into which data is got in synchronization with a system clock will be shown.
FIG. 15 is a circuit diagram showing an example of conventional circuits for transferring data. FIG. 16 is a view showing an example of the waveforms of data transferred under the single data rate method.
In the example shown in FIG. 15, the number of internal data buses 102 included in an output side device 100 is the same as that of internal data buses 103 included in an input side device 101. The number of external data buses 104 connected to the output side device 100 is the same as that of the external data buses 104 connected to the input side device 101. Command lines are also connected to the output side device 100 and the input side device 101 on a one-to-one basis. Output latch circuits 105 and output buffer circuits 106 are located on the output side of the internal data buses 102 in the output side device 100. Input buffer circuits 107 and input latch circuits 108 are located on the input side of the internal data buses 103 in the input side device 101. A system clock is supplied to the output latch circuits 105 in the output side device 100 and the input latch circuits 108 in the input side device 101.
The output side device 100 transfers data and a command in synchronization with a system clock. That is to say, the output latch circuits 105 latch data from the internal data buses 102 and a command from the command lines at the leading edge of a system clock and send the data and command to the external data buses 104 and command lines, respectively, via the output buffer circuits 106. The input buffer circuits 107 in the input side device 101 accept the data and command transferred via the external data buses 104 and command lines respectively. Then the input latch circuits 108 latch and hold the data and command at the leading edge of the system clock and output them to the internal data buses 103.
The output side device 100 begins to output on the basis of the leading edge of the system clock. As shown in FIG. 16, however, delay D corresponding to a half cycle of the system clock is produced in data sent to the external data buses 104 to satisfy appropriate setup time the input side device 101 needs to get the data. As a result, the input side device 101 can latch data and command during the available period of the data and command with the timing of the leading edge of the system clock.
Usually data of a width processed by one command is sent by the internal data buses 102 and 103 and external data buses 104. If data of a width wider than the width of a bus is sent, one method is to divide the data among a plurality of clocks.
FIG. 17 is a view showing an example of the waveforms of data of a width twice the width of a bus which is transferred under the single data rate method.
If data of a width twice the width of a bus is transferred, the data corresponding to one command is divided between two clocks and is transferred. That is to say, the first half of the data, together with the command, is sent with the first clock and only the latter half of the data is sent with the second clock. If data of a width twice the width of a bus is transferred in this way under the single data rate method, another command cannot be issued (no operation is issued) while the latter half of the data is being sent. This will degrade the effective performance of a system.
In contrast, there are devices of a double data rate (DDR) type which can get data of a width twice the width of a bus not only with the leading edge of a clock signal but also with the trailing edge of the clock signal.
FIG. 18 is a circuit diagram showing an example of conventional output side devices of the double data rate type. FIGS. 19(A) and 19(B) are views showing an example of a latch pulse generation circuit. FIG. 19(A) is a circuit diagram of a latch pulse generation circuit. FIG. 19(B) is a view showing the waveforms of input to and output from the latch pulse generation circuit. FIG. 20 is a circuit diagram showing an example of a data selector.
It is assumed that an output side device 110 includes an internal data bus of a width of m bits. Then data is divided into two data blocks and is transferred with one cycle of a system clock. Therefore, the output side device 110 includes data selectors 111 with two input terminals A and B and one output terminal O. Input terminal A of each data selector 111 accepts data included in the first data block. Input terminal B of each data selector 111 accepts data included in the second data block. Output terminal O of each data selector 111 is connected to an external data bus 114 via a latch circuit 112 and output buffer 113. The total number of the external data buses 114 is m/2. The latch circuit 112 for latching data is controlled by a latch pulse generation circuit 115. The data selectors 111 and the latch pulse generation circuit 115 operate on the basis of a system clock, which is output via an output buffer as a synchronous signal (strobe signal).
As shown in FIG. 19, the latch pulse generation circuit 115 includes an AND gate 116 and NOR gate 117. One input terminal of the AND gate 116 and one input terminal of the NOR gate 117 are connected directly to a system clock. The other input terminal of the AND gate 116 and the other input terminal of the NOR gate 117 are connected to output of an inverter 118. A delay circuit 119 for adjusting the width of a latch pulse which inputs and delays a system clock is connected to input of the inverter 118. Output of the AND gate 116 and NOR gate 117 is connected to input of an OR gate 120. Output from the OR gate 120 is output from the latch pulse generation circuit 115.
In the latch pulse generation circuit 115 the AND gate 116 outputs latch pulse a in response to the leading edge of a system clock and the NOR gate 117 outputs latch pulse b in response to the trailing edge of the system clock. The widths of latch pulses a and b correspond to delay time created by the delay circuit 119.
As shown in FIG. 20, the data selector 111 includes NAND gates 121 and 122. The input terminal A of the data selector 111 is connected to one input terminal of the NAND gate 121 and the input terminal B of the data selector 111 is connected to one input terminal of the NAND gate 122. Output of the NAND gates 121 and 122 is connected to input of a NAND gate 123. Output of the NAND gate 123 is connected to the output terminal O of the data selector 111. The other input terminal of the NAND gate 121 is connected directly to a system clock and the other input terminal of the NAND gate 122 is connected to output of an inverter 124 which accepts the system clock at the input.
When a system clock is at the low level in the data selector 111, the NAND gate 121 permits data input from the input terminal A and the NAND gate 122 prohibits data input from the input terminal B. In contrast, when a system clock is at the high level, the NAND gate 121 prohibits data input from the input terminal A and the NAND gate 122 permits data input from the input terminal B.
In the output side device 110 having the above structure, the data selectors 111 alternately select data 0 through m/2-1, respectively, included in a first half data block and data m/2 through m-1, respectively, included in a second half data block every half cycle of a system clock. The latch circuits 112 latch data 0 through m/2-1, respectively, included in the first half data block in response to latch pulse a from the latch pulse generation circuit 115 and output them to the external data buses 114 via the output buffers 113. Moreover, the latch circuits 112 latch data m/2 through m-1, respectively, included in the second half data block in response to latch pulse b and output them to the external data buses 114 via the output buffers 113.
FIG. 21 is a circuit diagram showing an example of conventional input side devices of the double data rate type. FIGS. 22(A) and 22(B) are views showing an example of a latch pulse generation circuit. FIG. 22(A) is a circuit diagram of a latch pulse generation circuit. FIG. 22(B) is a view showing the waveforms of input to and output from the latch pulse generation circuit.
In an input side device 130 data is accepted by input buffers 131. Output of each input buffer 131 is connected to input of two latch circuits 132. Control input of one of each pair of latch circuits 132 is connected to one output terminal c of a latch pulse generation circuit 133. Control input of the other of each pair of latch circuits 132 is connected to the other output terminal d of the latch pulse generation circuit 133.
As shown in FIG. 22, the latch pulse generation circuit 133 includes an AND gate 134 and NOR gate 135. One input terminal of the AND gate 134 and one input terminal of the NOR gate 135 are connected directly to a system clock. The other input terminal of the AND gate 134 and the other input terminal of the NOR gate 135 are connected to output of an inverter 136. A delay circuit 137 for adjusting the width of a latch pulse which inputs and delays a system clock is connected to input of the inverter 136. Output of the AND gate 134 is connected to a delay circuit 138 for adjusting setup time. Output of the delay circuit 138 is the output c of the latch pulse generation circuit 133. Output of the NOR gate 135 is connected to input of a delay circuit 139 for adjusting setup time. Output of the delay circuit 139 is the output d of the latch pulse generation circuit 133.
In the latch pulse generation circuit 133 the AND gate 134 outputs a latch pulse in response to the leading edge of a synchronous signal. This latch pulse is delayed by the delay circuit 138 and is output from the output c. The NOR gate 135 outputs a latch pulse in response to the trailing edge of the synchronous signal. This latch pulse is delayed by the delay circuit 139 and is output from the output d.
In the input side device 130 having the above structure, the latch pulse generation circuit 133 generates a first latch pulse during the period for which a synchronous signal is at the low level, and generates a second latch pulse during the period for which the synchronous signal is at the high level. The latch circuits 132 alternately latch data which they accepted via the input buffers 131 in response to these first and second latch pulses. By doing so, data included in a first half data block and data included in a second half data block are allotted to internal data buses. That is to say, the latch circuits 132 which operate by a latch pulse from the output c of the latch pulse generation circuit 133 get data 0 through m/2-1, respectively, included in the first half data block and the latch circuits 132 which operate by a latch pulse from the output d of the latch pulse generation circuit 133 get data m/2 through m-1, respectively, included in the second half data block.
As stated above, the amount of data which a device of the double data rate type can transfer during one cycle of a system clock is twice the amount of data which a device of the single data rate type can transfer. With devices of the double data rate type, a command is usually got only at the leading edge of a system clock and data is got twice by one command.
The data transfer rate of a device of the double data rate type is twice the data transfer rate of a device of the single data rate type. As a result, the available period of data for a device of the double data rate type is half of the available period of data for a device of the single data rate type and setup time for a clock for getting data for a device of the double data rate type is also half of setup time for a clock for getting data for a device of the single data rate type. However, the characteristics of a pull-up transistor and pull-down transistor in a driver for driving a clock are not necessarily the same in some operating environments. This makes it difficult to keep setup time and hold time at the time of getting data optimal.
Furthermore, if data is divided into n blocks and is transferred, the head of the data must be realized correctly to rearrange the n blocks transferred. This applies both to a device of the single data rate type and to a device of the double data rate type. Usually an effective command or the like, together with the leading data, is transferred to indicate the head of data. In this case, however, a circuit for interpreting the command and generating a data latch signal gets complicated.